/*
utf-8
------------------------------------------------
数码管扫描显示模块
------------------------------------------------
*/
module display (
	input clk,							//1kHz
	input wire [23:0] time_byte,		//数码管显示输入二进制
	input wire [5:0]	dp_in,			//小数点输入
	output wire [7:0] display_Pins,		//共阳极输入字段，对应a,b,c,d,e,f,g,dp
	output reg [5:0] contral_Pins		//数码管控制引脚，从左到右对应
);

	reg [2:0] count = 0;
	reg [3:0] in;
	reg temp1;
	wire [6:0] temp2;

	assign display_Pins = {~temp2, temp1};

	always @(posedge clk) begin
		if(count == 5)
			count = 0;
		else
			count = count + 1'b1;
	end

	always @(count)
	case(count)
		0:begin 
			contral_Pins <= 6'b011111;
			in <= time_byte[23:20]; 
			temp1 <= ~dp_in[5];
			end
		1:begin 
			contral_Pins <= 6'b101111;
			in <= time_byte[19:16]; 
			temp1 <= ~dp_in[4];
			end
		2:begin 
			contral_Pins <= 6'b110111;
			in <= time_byte[15:12]; 
			temp1 <= ~dp_in[3];
			end
		3:begin 
			contral_Pins <= 6'b111011;
			in <= time_byte[11:8]; 
			temp1 <= ~dp_in[2];
			end
		4:begin 
			contral_Pins <= 6'b111101;
			in <= time_byte[7:4]; 
			temp1 <= ~dp_in[1];
			end
		5:begin 
			contral_Pins <= 6'b111110;
			in <= time_byte[3:0]; 
			temp1 <= ~dp_in[0];
			end
		default begin contral_Pins <= 6'b111111;end
	endcase

	BCD7 u_BCD7(
		.in (in ),
		.a  (temp2[6]  ),
		.b  (temp2[5]  ),
		.c  (temp2[4]  ),
		.d  (temp2[3]  ),
		.e  (temp2[2]  ),
		.f  (temp2[1]  ),
		.g  (temp2[0]  )
	);
	
	
endmodule


/*
module display_old(clk,HH,HL,MH,ML,SH,SL,dp_in,a,b,c,d,e,f,g,dp,conHH,conHL,conMH,conML,conSH,conSL);

	input clk;
	input[5:0] dp_in;
	input[3:0] HH,HL,MH,ML,SH,SL;
	output a,b,c,d,e,f,g,dp;
	output conHH,conHL,conMH,conML,conSH,conSL;
	reg[2:0] count = 0;
	reg conHH,conHL,conMH,conML,conSH,conSL;
	reg[3:0] in;
	reg dp;
	reg SET_HH = 1,SET_HL = 1,SET_MH = 1,SET_ML = 1;
	wire Ya,Yb,Yc,Yd,Ye,Yf,Yg;

	assign {a,b,c,d,e,f,g} = ~{Ya,Yb,Yc,Yd,Ye,Yf,Yg};
	
	BCD7 display(.in(in),.a(Ya),.b(Yb),.c(Yc),.d(Yd),.e(Ye),.f(Yf),.g(Yg));
	
	clk_50MHz_1kHz clk_50MHz_1kHz
	(
	.clk_50MHz		(clk),
	.clk_1kHz			(clk_1kHz)
	);
	
	always @(posedge clk_1kHz)
	begin
		if(count == 5)
			count = 0;
		else
			count = count + 1;
	end
	

	
	always @(count)
	case(count)
		0:begin 
			{conHH,conHL,conMH,conML,conSH,conSL} <= 6'b011111;
			in <= HH; 
			dp <= ~dp_in[5];
			end
		1:begin 
			{conHH,conHL,conMH,conML,conSH,conSL} <= 6'b101111;
			in <= HL; 
			dp <= ~dp_in[4];
			end
		2:begin 
			{conHH,conHL,conMH,conML,conSH,conSL} <= 6'b110111;
			in <= MH; 
			dp <= ~dp_in[3];
			end
		3:begin 
			{conHH,conHL,conMH,conML,conSH,conSL} <= 6'b111011;
			in <= ML; 
			dp <= ~dp_in[2];
			end
		4:begin 
			{conHH,conHL,conMH,conML,conSH,conSL} <= 6'b111101;
			in <= SH; 
			dp <= ~dp_in[1];
			end
		5:begin 
			{conHH,conHL,conMH,conML,conSH,conSL} <= 6'b111110;
			in <= SL; 
			dp <= ~dp_in[0];
			end
		default begin {conHH,conHL,conMH,conML,conSH,conSL} <= 6'b111111;end
	endcase

	
	
	

endmodule

*/

module BCD7(in,a,b,c,d,e,f,g); //一位数码管显示
  input[3:0] in;
  output a,b,c,d,e,f,g;
  reg a,b,c,d,e,f,g;
  
  always @(in)
	case(in)
								 //abcdefg
		4'b0000:{a,b,c,d,e,f,g}=7'b1111110;//0
		4'b0001:{a,b,c,d,e,f,g}=7'b0110000;//1 
		4'b0010:{a,b,c,d,e,f,g}=7'b1101101;//2
		4'b0011:{a,b,c,d,e,f,g}=7'b1111001;//3
		4'b0100:{a,b,c,d,e,f,g}=7'b0110011;//4
		4'b0101:{a,b,c,d,e,f,g}=7'b1011011;//5
		4'b0110:{a,b,c,d,e,f,g}=7'b1011111;//6
		4'b0111:{a,b,c,d,e,f,g}=7'b1110000;//7
		4'b1000:{a,b,c,d,e,f,g}=7'b1111111;//8
		4'b1001:{a,b,c,d,e,f,g}=7'b1111011;//9
		
		4'b1010:{a,b,c,d,e,f,g}=7'b0000001;//-
		4'b1011:{a,b,c,d,e,f,g}=7'b1000111;//F
		4'b1100:{a,b,c,d,e,f,g}=7'b0011101;//o
		4'b1101:{a,b,c,d,e,f,g}=7'b1110111;//A
		4'b1110:{a,b,c,d,e,f,g}=7'b1100111;//P
		4'b1111:{a,b,c,d,e,f,g}=7'b0000000;
	endcase
 
endmodule
